The invention relates to a programmable sequence controller in which a general purpose microprocessor such as a microcomputer chip relatively low in processing rate is employed in a translational mode to cyclically and successively process a series of sequence control data.
In general, in a conventional programmable sequence controller of this type, a minicomputer having a microprogramming function is employed as its central processing unit, the sequence dedication language is translated into process routines by using the instruction words of the mini-computer in advance, and the sequence execution is effected in the translational mode by successively applying the program loops of the sequence dedication language to the respective process routines.
The arrangement and operation of one example of such a conventional programmable sequence controller will be described.
The arrangement of this type of conventional programmable sequence controller is as shown in FIG. 1. The programmable sequence controller includes a central processing unit 1 (hereinafter referred to merely as "a CPU 1" when applicable), a microprogram memory 2, a sequence program memory 3, and a scratch pad memory 4.
The CPU 1 is capable of carrying out 8-bit or 16 bit parallel logic or arthmetic operations. In the conventional controller of the present example, a CPU capable of 8-bit parallel processing is employed.
The microprogram memory 2 is a high speed read only memory (ROM). Stored in the microprogram memory 2 are a microprogram 2A which is a set of microinstructions corresponding to sequence instructions for decoding and executing sequence dedication language and an operation procedure program 2B which functions as a sequence controller.
The sequence program memory 3 is a non-volatile memory such as a core memory the stored contents of which can be changed by writing. The function of sequence program memory 3 is to store a sequence program in which each sequence control step of a process to be controlled by the sequence controller is described in the sequence dedication language of the sequence controller.
The scratch pad memory may be either a non-volatile memory such as a core memory or a volatile memory such as a semiconductor memory. The scratch pad memory is an assembly of memories adapted to store the results of the processing steps for sequence control in real time or an assembly of memories adapted to store flags which indicate the present amount of data in a counter and a timer operated by software by indicating that the counter and the timer are in a filled-up state.
The programmable sequence controller further includes a plurality of contact means 9 which have been set to indicate states corresponding to a process which is externally controlled (hereinafter referred to as "external contact means 9" when applicable), a multiplexer 7 for selecting from eight optional external contact means 9A as specified by an address bus 101 of the CPU 1 by way of the external contact means 9, and an input buffer 5 made up of eight flip-flops. The input buffer 5 stores the on/off states of the external contact means 9A which have been selected by the multiplexer 7 upon a latch instruction on line 103 from the CPU 1. The stored contents 108 of the input buffer 5 are coupled through the data bus 102 to its corresponding CPU 1.
Plural output buffers 6 are provided, each including eight flip-flops. A demultiplexer 8 operates to select a single optional output buffer 6A which has been specified by the address bus 101 of the CPU 1 out of the set of output buffers 6. Upon receipt of a latch instruction on line 103 from the CPU 1, the demultiplexer 8 generates a latch instruction on line 109 which gates the latch instruction on line 103 from the CPU 1 solely to the particular output buffer 6A thus selected while allowing the output buffer 6A to retain the contents of the data bus 102 at that moment.
In FIG. 1, reference numeral 10 designates output relays which amplify the contents 110 of the output buffers 6 by means of amplifiers (not shown) which provide increased driving capability. The contact outputs of the output relays 10 are applied as the outputs of the sequence controller for operating the external process which is operated and controlled in accordance with the on/off states of the output relays 10.
A programming panel 11 is provided with a keyboard, display lamps, a digit display device, etc as desired. The programming panel 11 is connected to the address bus 101 and the data bus 102 of the CPU 1. The programming panel 11 accesses the sequence program memory 3, the scratch pad memory 4, the input buffer 5 and the output buffer 6 through the bus lines 101 and 102 so that a desired sequence program is written into the sequence program memory 3 by means of the keyboard while the contents of the sequence program memory 3 and the scratch pad memory 4 and the states of the external contacts 9 and the output relays 10 are read and the results thus read are indicated to the operator by means of the display lamps and the digit display mechanism.
The programmable sequence controller further includes a reading/writing control line 104 for applying a reading/writing control signal generated by the CPU 1 or the programming panel 11, a bus request signal line 105 for supplying a bus request signal which indicates a request for using the reading/writing line 104 to the CPU 1 from the programming panel 11, and a bus request acknowledge signal line 106 for supplying a bus request acknowledge signal which indicates to the programming panel 11 that the address bus 101, the data bus 102 and the reading/writing control line 104 have been disconnected from the CPU 1. The bus request acknowledge signal is provided by the CPU 1 in response to the bus request signal.
The operation of the conventional sequence controller of FIG. 1 thus organized will be described with reference to FIG. 2 which is a flow chart showing the contents and operation of the operation procedure program 2B of the sequence controller which is stored in the microprogram memory 2.
In the sequence controller, when the power switch is turned on or in response to a start-up operation procedure the CPU 1 resets the sequence program count 1B therein which has been specified by the microprogram 2A.
Next, a part of the contents of the sequence program memory 3 which corresponds to one step in sequence control of the externally controlled process is read out by the operation procedure program 2B with the contents of the sequence program counter 1B as the reading address. The contents thus read are discriminated in accordance with the operational procedure of program 2B. The sequence instruction for one step thus read is executed according to the microprogram 2A.
Sequence instructions stored in the sequence program memory 3 are indicated in FIG. 3. That is, those instructions are three different sequence control instructions, an input instruction 3A, an output instruction 3B, and a logic operation instruction 3C. An END instruction 3D is stored at the end of a series of these sequence control instructions 3A, 3B and 3D to indicate the completion of a series of sequential operations.
When the sequence control instruction read out of the sequence program memory 3 by the CPU 1 is the input instruction 3A, the CPU 1 transfers the required data into the accumulator 1A in the CPU 1 from the input address specified by the input instruction 3A.
In other words, in the case that the address of the input destination specified by the input instruction 3A is an address of the external contact 9, the CPU 1 applies the address thus specified to the address bus 101 so as to cause the multiplexer 7 to select the external contact 9A specified by the address bus 101. Then, when the latch command 103 is issued, the on/off state of the external contact 9A selected at that moment is stored in the flip-flops of the input buffer 5. The contents thus stored in the input buffer 5 are written into the accumulator 1A of the CPU 1 through the data bus 102. At this point, reading the on/off state of an external contact 9A by the CPU has been completed.
In the case where the address of the input destination specified by the input instruction 3A is an address in the scratch pad memory 4, the address thus specified is applied to the address bus 101 similarly while the contents of the address thus specified in the scratch pad memory 4 is coupled into the accumulator 1A in the CPU directly through the data bus 103. Thus, in this fashion, the contents of the counter, the state of the timer, and the state of the flag which have been stored in the scratch pad memory 4 are read by the accumulator 1A of the CPU 1.
In the case that the sequence control instruction read is the output instruction, the CPU 1 applies the address of the output destination specified by the output instruction to the address bus 101 and the contents of the accumulator 1A and transfers it to the data bus 102 after which the latch command 103 is issued. According to what is indicated on the address bus 102, the demultiplexer 8 selects one (6A) of the output buffers 6. A latch command 109 obtained by gating the latch command 103 from the CPU 1 through the demultiplexer 7 is applied only to the particular output buffer 6A thus selected and the contents of the data bus 102 at that moment, namely, the contents of the accumulator 1A, are stored in the output buffer 6A selected. The contents stored in the output buffer 6A are coupled through the output relay 10 for operating the externally controlled process.
In the case that the sequence control instruction read is a logic operation instruction 3C, the CPU 1 carries out an operation similar to that in the case that the input instruction is read and, accordingly, the operand for operation is applied to the data bus. Thereafter, an operation specified by the logic operation instruction 3C is carried out with respect to the contents of the data bus 102 and the contents of the accumulator 1A with the result of the operation becoming the contents of the accumulator 1A.
Wherever any one step of a sequence control instruction, that is, a single step operation of the input instruction 3A, output instruction 3B or logic operation instruction 3C, is completed, the CPU 1 advances by one step the contents of the sequence program counter 1B according to the instructions of the microprogram 2A so as to read and execute the next step of the sequence program memory 3. Thereafter, as this operation is repeatedly carried out, the contents of the sequence program memory 3 are successively executed.
In the case that the sequence instruction read out of the sequence program memory 3 by the CPU 1 is the END instruction 3D, the sequence counter 1B is reset. Accordingly, the CPU 1 successively reads step-by-step the sequence control instructions 3A, 3B and 3C stored in the sequence program memory 3 and advances the sequence control while repeating the execution of the contents thereof.
Described next are the operations of rewriting the contents of the sequence program memory 3 by means of the programming panel 11 and reading the contents of the sequence program memory 3 and the scratch pad memory 4, the input and output state (the on/off states 107 of the external contents 9), and the contents 110 of the output buffers 6 by means of the programming panel 11.
First, the bus request signal is sent from the programming panel 11 to the CPU 1 which has executed the above-described sequence. Upon receipt of the bus request signal, the CPU temporarily stops its operation after completing the execution of the step of micro-instruction which is then being executed. Then, the CPU 1 releases the address bus 101, the data bus 102 and the reading/writing control line 104 by disconnecting those bus lines from its control lines. Subsequently, the CPU 1 sends the bus request acknowledge signal to the programming panel 11 through the bus request acknowledge signal line 106.
Upon receipt of the bus request acknowledge signal, the programming panel 11 uses the address bus 101, the data bus 102 and the reading/writing control line 104, now disconnected from the control lines of the CPU 1, to rewrite the contents of the sequence program memory 3.
The programming panel 11 has as one of its functions the reading of the input and output states 107 and 110 with respect to the externally controlled process and the contents of the sequence program memory 3 and the scratch pad memory 4 and displaying the data thus read on the programming panel 11, as required. The operation of the sequence program panel 11 will not be described because it operates completely the same as the above-described operation of rewriting the contents of the sequence program memory 3.
Upon completion of the above-described reading/writing operation, the programming panel 11 interrupts the application of the bus request signal to the CPU 1 on the bus request signal line 105 and disconnects the address bus 101, the data bus 102 and the reading/writing control line 104. When the application of the bus request signal is interrupted, the CPU 1 turns off the bus request acknowledge signal issued on the bus request acknowledge signal line 106, returns to its operational state from its halted state, and starts again the execution of the sequence control operation beginning with the next step in sequence which had not been executed because of the receipt of the bus request signal.
With a conventional programmable sequence controller thus organized in which a general purpose computer is operated in a translation mode, the micro-instruction processing speed of the computer must be high, less than 1 to 2 .mu.sec, in order to process a required thousand or so steps at a response speed equivalent to that of the sequence control using ordinary relays.
With respect to this requirement, no particular difficulty is encountered if a microprocessor such as a minicomputer utilizing bipolar semiconductor device elements is employed as the CPU. However, if a computer having a lower processing rate as, for example, a microcomputer chip utilizing an MOS-type process, is used as the CPU, then the response speed is undesirably reduced to 1/4 to 1/10 of the response speed compared to the case where bipolar elements are employed. The microprocessing speed is considerably lower, for instance 4 to 10 .mu.sec.
In a conventional sequence controller, if the programming panel is operated while the CPU is executing a sequence program, the CPU must temporarily suspend its operation. Therefore, such a conventional sequence controller is disadvantageous in that the speed of execution of the sequence program, that is, the response speed thereof, is further decreased.
Furthermore, in general, in an ordinary microcomputer chip, the processing speed of the input instruction/output instruction for the outside is reduced to about 1/1.5 to 1.2 of the processing speed for the input and output instructions for the memories. Accordingly, in a method in which, as in the above-described conventional sequence controller, a relatively high number of input instructions/output instructions to the outside must be used, the processing speed is further decreased. This further exasperates the problems involved in using a microcomputer chip lower in speed and in cost as the CPU of the sequence controller.